13-迅为iTOP-4412精英版之linux内核移植
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准备工作
虚拟机：VM-Ware 16.2.3
操作系统：Ubuntu Linux 16.04
交叉编译器：arm-linux-gcc-4.6.4
工作文件夹：/home/work
搭建配置好交叉编译环境，完整搭建配置过程可参照下述博文：
迅为iTOP-4412之Android 4.0系统编译环境的搭建（完整版）_itop-4412启动的安卓界面-CSDN博客
提示：虚拟机中解压完后的原打包文件建议删除，可以节约虚拟机空间。
一、linux内核源码的获取
1、从linux官网下载内核源码
从linux 官方网站：https://www.kernel.org/ ，下载内核源码，我们选择的是linux4.14.326，如下图所示：
单击打包“tarball”（将多个文件打包成一个文件称之为tarball），进行内核源码的下载，如下图所示：
内核源码文件linux-4.14.326.tar.xz下载完成，如下图所示：
2、虚拟机中解压内核源码
下载完成后，打开虚拟机，在虚拟机Ubuntu中的“/home/work”文件夹中建立"kernel"目录文件夹，并将下载的内核源码压缩包linux-4.14.326.tar.xz拷贝进去，操作过程如下图所示：
说明：有关 .tar.xz打包文件的解压说明
tar.xz是一种文件压缩格式，其中tar是一个类Unix操作系统下的文件归档格式，用于将多个文件打包成一个文件，称之为tarball，使用tarball可以方便地进行传输、备份、存档或者用于其他目的。而xz则是一种无损数据压缩工具，采用 LZMA/LZMA2 压缩算法，可以压缩文件到很小的大小。
因此，tar.xz文件是对多个文件进行归档后再进行压缩得到的一个包含所有文件的文件。在Ubuntu操作系统中，用于解压tar.xz文件的工具为tar命令和unxz命令，咱们以tar命令来进行解压并说明。
使用tar命令解压tar.xz文件需要使用到两个参数，首先-tar选项用于指定要执行的操作，然后-f选项指定要操作的文件名，使用"-"号表示从标准输入读取文件或者将文件输出到标准输出。
回到本文正题，需要将该打包文件压缩到/home/work/kernel下，如上图所示，/home/work/kernel是当前目录，只需解压到当前目录即可，命令如下：
tar -xvf linux-4.14.326.tar.xz其中，-x选项表示解压文件，-v选项用于输出详细信息，-f选项指定要操作的文件名，可以将文件名替换成实际的文件名。
解压完成，生成linux-4.14.326文件夹，如下图所示：
二、修改源码编译架构及编译器
打开Makefile文件：进入解压后的inux内核源码文件夹，查找Makefile文件夹，并用命令
gedit Makefile打开Makefile文件，过程如下图所示：
打开Makefile源文件后，打开显示行号“Display line numbers”，如下图所示：
修改320行和321行对应的架构（arch）和交叉编译器（CROSS_COMPILE），如下图所示：
提示：编译器要和前期配置源码编译环境过程中装的编译器统一，如果是arm-none-linux-gnueabi-编译器的话，则需修改如下：
Save保存关闭退出。
三、对内核进行裁剪
1、生成.config默认裁剪菜单文件
可以直接使用linux官方的默认配置即可，在内核源码下直接输入命令
make exynos_defconfig 如下图所示：
2、进入裁剪界面
配置平台和调试串口：在内核源码下输入命令
make menuconfig 试图打开裁剪界面。
如果出现报错提示，如下图所示：
根据上述提示，可知这个过程中需要ncurses库，但是在系统里面找不到，也就是基本的依赖库问题。解决方案就是安装一下 ncurses-devel就可以了，输入命令如下：
sudo apt-get install ncurses-dev
再次输入
make menuconfig成功打开裁剪界面，如下图所示：
3、选择芯片类型
下移选择" System Type "，回车，如下述图示所示：
下移选择“ Samsung EXYNOS ” 即迅为iTOP-4412开发板的内核型号“三星猎户座”，如下述图示所示：
回车进入该路径的选项配置，在配置过程中，【*】的选择和【 】的取消用“空格键”来进行操作，最终配置成下图所示：
4、调试串口的配置
右移到“Exit”，回车返回到“menuconfig”第一级目录，从第一级目录下移找到“ Kernel hacking ”的内核监视路径。
回车进入到“ Kernel hacking”的内核监视路径，选中“Kernel low-level debugging functions (read help!)”和“Early printk”两个选项，如下图所示：
然后选择“Kernel low-level debugging port (Use Samsung S3C UART 0 for low-level debug) ” 选项，把串口设置成串口2，如下图所示:：
5、文件系统启动方式的配置
返回到menuconfig第一级目录，从第一级目录选择“Boot options”，如下图所示：
回车，进入“ Boot options”，进行配置，如下图所示：
进入上图中第二个红框标注的中间一行，进行内核启动参数的设置，将其设置为
root=/dev/mmcblk0p2 rw console=ttySAC2,115200 init=/linuxrc rootwait 如下图所示：
保存退出，继续将Kernel command type改为：kernel模式，如下图所示：
修改好后，结果如下图所示：
6、网络的配置
itop4412开发板板载dm9621网卡芯片是usb类型，因此需要依赖于usb 网络框架，所以要通过裁剪菜单选中支持项。
返回到menuconfig第一级目录，从第一级目录选择“Device Drivers”，如下图所示：
进入到设备驱动选项后，选择“Network device support ”网络设备支持选项，如下图所示：
进入网络设备支持选项后，选择USB网络适配，如下图所示：
进入USB网络适配设置，在其下选择对DM96XX的支持，如下图所示：
7、配置NFS服务
返回到menuconfig第一级目录，从第一级目录选择“File systems ”文件系统选项，如下图所示：
进入文件系统，继续选择网络文件系统选项，如下图所示：
进入网络文件系统，在网络文件系统配置界面，选中和NFS相关的选项，如下图所示：
设置完成后，保存并退出menuconfig配置。
四、对内核进行编译
1、编译命令及结果
我们在内核源码目录下输入以下命令：
make uImage LOADADDR=0X40007000编译过程需要几分钟的时间，其中“ LOADADDR=0X40007000 ” 表示指定内核的加载地址，编译成功如下图所示：
2、编译失败问题处理
1）如果系统配置的是厂家提供的 “ arm-2009q3 ”编译器，内核编译时如提示如下错误信息：
/linux-4.14.326# make uImage LOADADDR=0X40007000
scripts/kconfig/conf --silentoldconfig Kconfig
CHK include/config/kernel.release
CHK include/generated/uapi/linux/version.h
CHK include/generated/utsrelease.h
CHK include/generated/bounds.h
CHK include/generated/timeconst.h
CHK include/generated/asm-offsets.h
CALL scripts/checksyscalls.sh
CHK scripts/mod/devicetable-offsets.h
CC init/main.o
/tmp/cc3vKZS1.s: Assembler messages:
/tmp/cc3vKZS1.s:1225: Error: unknown pseudo-op: `.arch_extension'
/tmp/cc3vKZS1.s:1226: Error: bad instruction `pldw [r3,#0]'
make[1]: *** [init/main.o] Error 1
make: *** [init] Error 2
root@ubuntu:/home/topeet/kernel/linux-4.14.326#
root@ubuntu:/home/topeet/kernel/linux-4.14.326#
主要由于交叉编译器版本与Linux 4.14内核兼容问题，只要将Makefile文件中第321行的编译器改成：arm-linux-gnueabi-
具体操作流程如下：
1. 清理之前的编译
make distclean2. 设置环境变量
内核源码目录下Makefile文件第320行还是arm不变，321行的编译器改成：arm-linux-gnueabi-
如果搜不到该编译器，则需要根据下面方法安装配置：
1.安装 ARM 交叉编译工具链:
在Ubuntu系统中,你可以通过以下命令安装:sudo apt-get update sudo apt-get install gcc-arm-linux-gnueabi2. 确认工具链安装成功:
安装完成后,检查是否能正常调用:arm-linux-gnueabi-gcc -- version如果能显示版本信息,说明安装成功。
3. 重新配置内核
make exynos_defconfig4. 重新编译
make uImage LOADADDR=0X40007000
2）如果编译不成功，出现 “mkimage“ command not found - U-Boot images will not be built” 的错误提示，如下图所示：
其实就是缺乏uboot工具，安装即可，安装命令如下：
sudo apt-get install u-boot-tools安装后，如下图所示：
安装成功后，再次输入编译内核命令，如下图所示：
2）如果编译不成功，出现 “arm-linux-gcc: Command not found" 的相关错误提示，如下图所示：
但是已经安装好交叉编译器了，还老是提示arm-linux-gcc找不到，其实是用户权限的问题，要确定make内核编译时和配置交叉编译器时是同一个root用户。
解决办法重新去用root权限进行交叉编译，再用root权限进行内核相关裁剪操作及内核编译。
交叉编译参考博文：ubuntun16.04下arm-linux-gcc交叉编译器的安装配置-CSDN博客
五、修改设备树（dts）文件
进到内核 arch/arm/boot/dts/下，里面默认有 iTOP 的设备树文件，如下所示：
cd arch/arm/boot/dts/
再找到iTOP4412三星猎户座内核匹配设备树文件，如下所示：
ls exynos4412-itop-*
打开编辑修改exynos4412-itop-scp-core.dtsi文件，如下所示：
gedit exynos4412-itop-scp-core.dtsi
1、注释掉firmware设备
firmware是三星的一个固件的设备信息，因为找不到固件，所以内核启动不成功。注释掉29到32行的代码，如下图所示：
2、修改event属性
因为没有events这个属性，所以我们要把72行的events修改成event,如下图所示：
3、配置核心板电源芯片
Exynos4412 芯片的POP和SCP两种封装形式，芯片的电源管理都是低功耗动态三星 S5M8767 电源管理架构。
把下面的代码修改成如下图所示：
CTRL+S，CTRL+Q，保存退出。
/*
* TOPEET's Exynos4412 based itop board device tree source
*
* Copyright (c) 2016 SUMOMO Computer Association
* https://www.sumomo.mobi
* Randy Li <ayaka@soulik.info>
*
* Device tree source file for TOPEET iTop Exynos 4412 SCP package core
* board which is based on Samsung's Exynos4412 SoC.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/clock/samsung,s2mps11.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "exynos4412.dtsi"
#include "exynos4412-ppmu-common.dtsi"
#include "exynos-mfc-reserved-memory.dtsi"
/ {
memory@40000000 {
device_type = "memory";
reg = <0x40000000 0x40000000>;
};
//firmware@0203F000 {
// compatible = "samsung,secure-firmware";
// reg = <0x0203F000 0x1000>;
//};
fixed-rate-clocks {
xxti {
compatible = "samsung,clock-xxti";
clock-frequency = <0>;
};
xusbxti {
compatible = "samsung,clock-xusbxti";
clock-frequency = <24000000>;
};
};
thermal-zones {
cpu_thermal: cpu-thermal {
cooling-maps {
map0 {
/* Corresponds to 800MHz at freq_table */
cooling-device = <&cpu0 7 7>;
};
map1 {
/* Corresponds to 200MHz at freq_table */
cooling-device = <&cpu0 13 13>;
};
};
};
};
usb-hub {
compatible = "smsc,usb3503a";
reset-gpios = <&gpm2 4 GPIO_ACTIVE_LOW>;
connect-gpios = <&gpm3 3 GPIO_ACTIVE_HIGH>;
intn-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&hsic_reset>;
};
};
&bus_dmc {
devfreq-event = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>;
vdd-supply = <&buck1_reg>;
status = "okay";
};
&bus_acp {
devfreq = <&bus_dmc>;
status = "okay";
};
&bus_c2c {
devfreq = <&bus_dmc>;
status = "okay";
};
&bus_leftbus {
devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>;
vdd-supply = <&buck3_reg>;
status = "okay";
};
&bus_rightbus {
devfreq = <&bus_leftbus>;
status = "okay";
};
&bus_fsys {
devfreq = <&bus_leftbus>;
status = "okay";
};
&bus_peri {
devfreq = <&bus_leftbus>;
status = "okay";
};
&bus_mfc {
devfreq = <&bus_leftbus>;
status = "okay";
};
&cpu0 {
cpu0-supply = <&buck2_reg>;
};
&hsotg {
vusb_d-supply = <&ldo15_reg>;
vusb_a-supply = <&ldo12_reg>;
};
&i2c_1 {
#address-cells = <1>;
#size-cells = <0>;
samsung,i2c-sda-delay = <100>;
samsung,i2c-max-bus-freq = <400000>;
pinctrl-0 = <&i2c1_bus>;
pinctrl-names = "default";
status = "okay";
s5m8767: s5m8767-pmic@66 {
compatible = "samsung,s5m8767-pmic";
reg = <0x66>;
s5m8767,pmic-buck-default-dvs-idx = <3>;
s5m8767,pmic-buck-dvs-gpios = <&gpb 5 GPIO_ACTIVE_HIGH>,
<&gpb 6 GPIO_ACTIVE_HIGH>,
<&gpb 7 GPIO_ACTIVE_HIGH>;
s5m8767,pmic-buck-ds-gpios = <&gpm3 5 GPIO_ACTIVE_HIGH>,
<&gpm3 6 GPIO_ACTIVE_HIGH>,
<&gpm3 7 GPIO_ACTIVE_HIGH>;
/* VDD_ARM */
s5m8767,pmic-buck2-dvs-voltage = <1356250>, <1300000>,
<1243750>, <1118750>,
<1068750>, <1012500>,
<956250>, <900000>;
/* VDD_INT */
s5m8767,pmic-buck3-dvs-voltage = <1000000>, <1000000>,
<925000>, <925000>,
<887500>, <887500>,
<850000>, <850000>;
/* VDD_G3D */
s5m8767,pmic-buck4-dvs-voltage = <1081250>, <1081250>,
<1025000>, <950000>,
<918750>, <900000>,
<875000>, <831250>;
regulators {
ldo1_reg: LDO1 {
regulator-name = "VDD_ALIVE";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
};
/* SCP uses 1.5v, POP uses 1.2v */
ldo2_reg: LDO2 {
regulator-name = "VDDQ_M12";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
};
ldo3_reg: LDO3 {
regulator-name = "VDDIOAP_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
op_mode = <1>; /* Normal Mode */
};
ldo4_reg: LDO4 {
regulator-name = "VDDQ_PRE";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
op_mode = <1>; /* Normal Mode */
};
ldo5_reg: LDO5 {
regulator-name = "VDD_LDO5";
op_mode = <0>; /* Always off Mode */
};
ldo6_reg: LDO6 {
regulator-name = "VDD10_MPLL";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
op_mode = <1>; /* Normal Mode */
};
ldo7_reg: LDO7 {
regulator-name = "VDD10_XPLL";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
op_mode = <1>; /* Normal Mode */
};
ldo8_reg: LDO8 {
regulator-name = "VDD10_MIPI";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
op_mode = <1>; /* Normal Mode */
};
ldo9_reg: LDO9 {
regulator-name = "VDD33_LCD";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
op_mode = <1>; /* Normal Mode */
};
ldo10_reg: LDO10 {
regulator-name = "VDD18_MIPI";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
op_mode = <1>; /* Normal Mode */
};
ldo11_reg: LDO11 {
regulator-name = "VDD18_ABB1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
op_mode = <1>; /* Normal Mode */
};
ldo12_reg: LDO12 {
regulator-name = "VDD33_UOTG";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
op_mode = <1>; /* Normal Mode */
};
ldo13_reg: LDO13 {
regulator-name = "VDDIOPERI_18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
op_mode = <1>; /* Normal Mode */
};
ldo14_reg: LDO14 {
regulator-name = "VDD18_ABB02";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
op_mode = <1>; /* Normal Mode */
};
ldo15_reg: LDO15 {
regulator-name = "VDD10_USH";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
op_mode = <1>; /* Normal Mode */
};
ldo16_reg: LDO16 {
regulator-name = "VDD18_HSIC";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
op_mode = <1>; /* Normal Mode */
};
ldo17_reg: LDO17 {
regulator-name = "VDDIOAP_MMC012_28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
op_mode = <1>; /* Normal Mode */
};
/* Used by HSIC */
ldo18_reg: LDO18 {
regulator-name = "VDDIOPERI_28";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
op_mode = <1>; /* Normal Mode */
};
ldo19_reg: LDO19 {
regulator-name = "VDD_LDO19";
op_mode = <0>; /* Always off Mode */
};
ldo20_reg: LDO20 {
regulator-name = "VDD28_CAM";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
op_mode = <1>; /* Normal Mode */
};
ldo21_reg: LDO21 {
regulator-name = "VDD28_AF";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
op_mode = <1>; /* Normal Mode */
};
ldo22_reg: LDO22 {
regulator-name = "VDDA28_2M";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
op_mode = <1>; /* Normal Mode */
};
ldo23_reg: LDO23 {
regulator-name = "VDD28_TF";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
op_mode = <1>; /* Normal Mode */
};
ldo24_reg: LDO24 {
regulator-name = "VDD33_A31";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
op_mode = <1>; /* Normal Mode */
};
ldo25_reg: LDO25 {
regulator-name = "VDD18_CAM";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
op_mode = <1>; /* Normal Mode */
};
ldo26_reg: LDO26 {
regulator-name = "VDD18_A31";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
op_mode = <1>; /* Normal Mode */
};
ldo27_reg: LDO27 {
regulator-name = "GPS_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
op_mode = <1>; /* Normal Mode */
};
ldo28_reg: LDO28 {
regulator-name = "DVDD12";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
op_mode = <1>; /* Normal Mode */
};
buck1_reg: BUCK1 {
regulator-name = "vdd_mif";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
};
buck2_reg: BUCK2 {
regulator-name = "vdd_arm";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <1456250>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
};
buck3_reg: BUCK3 {
regulator-name = "vdd_int";
regulator-min-microvolt = <875000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
};
buck4_reg: BUCK4 {
regulator-name = "vdd_g3d";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
};
buck5_reg: BUCK5 {
regulator-name = "vdd_m12";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
};
buck6_reg: BUCK6 {
regulator-name = "vdd12_5m";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
op_mode = <1>; /* Normal Mode */
};
buck7_reg: BUCK7 {
regulator-name = "pvdd_buck7";
regulator-min-microvolt = <2050000>;
regulator-max-microvolt = <2050000>;
regulator-boot-on;
regulator-always-on;
op_mode = <1>; /* Normal Mode */
};
buck8_reg: BUCK8 {
regulator-name = "pvdd_buck8";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
regulator-always-on;
op_mode = <1>; /* Normal Mode */
};
buck9_reg: BUCK9 {
regulator-name = "vddf28_emmc";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <3000000>;
op_mode = <1>; /* Normal Mode */
};
};
s5m8767_osc: clocks {
#clock-cells = <1>;
clock-output-names = "s5m8767_ap",
"s5m8767_cp", "s5m8767_bt";
};
};
};
&mfc {
status = "okay";
};
&mshc_0 {
pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
pinctrl-names = "default";
status = "okay";
vmmc-supply = <&buck9_reg>;
broken-cd;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
samsung,dw-mshc-sdr-timing = <2 3>;
samsung,dw-mshc-ddr-timing = <1 2>;
bus-width = <8>;
cap-mmc-highspeed;
};
&pinctrl_1 {
hsic_reset: hsic-reset {
samsung,pins = "gpm2-4";
samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
samsung,pin-pud = <EXYNOS_PIN_PULL_NONE>;
samsung,pin-drv = <EXYNOS4_PIN_DRV_LV4>;
};
};
&rtc {
status = "okay";
clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>;
clock-names = "rtc", "rtc_src";
};
&tmu {
vtmu-supply = <&ldo16_reg>;
status = "okay";
};4、解决字符串溢出问题
打开编辑修改exynos4.dtsi文件，如下图所示：
注释掉文件中的串口2节点serial_2中的dmas属性，如下图所示：
保存退出。
/*
* Samsung's Exynos4 SoC series common device tree source
*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
* Copyright (c) 2010-2011 Linaro Ltd.
* www.linaro.org
*
* Samsung's Exynos4 SoC series device nodes are listed in this file. Particular
* SoCs from Exynos4 series can include this file and provide values for SoCs
* specfic bindings.
*
* Note: This file does not include device nodes for all the controllers in
* Exynos4 SoCs. As device tree coverage for Exynos4 increases, additional
* nodes can be added to this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <dt-bindings/clock/exynos4.h>
#include <dt-bindings/clock/exynos-audss-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "exynos-syscon-restart.dtsi"
/ {
interrupt-parent = <&gic>;
#address-cells = <1>;
#size-cells = <1>;
aliases {
spi0 = &spi_0;
spi1 = &spi_1;
spi2 = &spi_2;
i2c0 = &i2c_0;
i2c1 = &i2c_1;
i2c2 = &i2c_2;
i2c3 = &i2c_3;
i2c4 = &i2c_4;
i2c5 = &i2c_5;
i2c6 = &i2c_6;
i2c7 = &i2c_7;
i2c8 = &i2c_8;
csis0 = &csis_0;
csis1 = &csis_1;
fimc0 = &fimc_0;
fimc1 = &fimc_1;
fimc2 = &fimc_2;
fimc3 = &fimc_3;
serial0 = &serial_0;
serial1 = &serial_1;
serial2 = &serial_2;
serial3 = &serial_3;
};
clock_audss: clock-controller@03810000 {
compatible = "samsung,exynos4210-audss-clock";
reg = <0x03810000 0x0C>;
#clock-cells = <1>;
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
<&clock CLK_SCLK_AUDIO0>, <&clock CLK_SCLK_AUDIO0>;
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
};
i2s0: i2s@03830000 {
compatible = "samsung,s5pv210-i2s";
reg = <0x03830000 0x100>;
clocks = <&clock_audss EXYNOS_I2S_BUS>,
<&clock_audss EXYNOS_DOUT_AUD_BUS>,
<&clock_audss EXYNOS_SCLK_I2S>;
clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
#clock-cells = <1>;
clock-output-names = "i2s_cdclk0";
dmas = <&pdma0 12>, <&pdma0 11>, <&pdma0 10>;
dma-names = "tx", "rx", "tx-sec";
samsung,idma-addr = <0x03000000>;
#sound-dai-cells = <1>;
status = "disabled";
};
chipid@10000000 {
compatible = "samsung,exynos4210-chipid";
reg = <0x10000000 0x100>;
};
scu: snoop-control-unit@10500000 {
compatible = "arm,cortex-a9-scu";
reg = <0x10500000 0x2000>;
};
memory-controller@12570000 {
compatible = "samsung,exynos4210-srom";
reg = <0x12570000 0x14>;
};
mipi_phy: video-phy {
compatible = "samsung,s5pv210-mipi-video-phy";
#phy-cells = <1>;
syscon = <&pmu_system_controller>;
};
pd_mfc: mfc-power-domain@10023C40 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C40 0x20>;
#power-domain-cells = <0>;
label = "MFC";
};
pd_g3d: g3d-power-domain@10023C60 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C60 0x20>;
#power-domain-cells = <0>;
label = "G3D";
};
pd_lcd0: lcd0-power-domain@10023C80 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C80 0x20>;
#power-domain-cells = <0>;
label = "LCD0";
};
pd_tv: tv-power-domain@10023C20 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C20 0x20>;
#power-domain-cells = <0>;
power-domains = <&pd_lcd0>;
label = "TV";
};
pd_cam: cam-power-domain@10023C00 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023C00 0x20>;
#power-domain-cells = <0>;
label = "CAM";
};
pd_gps: gps-power-domain@10023CE0 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023CE0 0x20>;
#power-domain-cells = <0>;
label = "GPS";
};
pd_gps_alive: gps-alive-power-domain@10023D00 {
compatible = "samsung,exynos4210-pd";
reg = <0x10023D00 0x20>;
#power-domain-cells = <0>;
label = "GPS alive";
};
gic: interrupt-controller@10490000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x10490000 0x10000>, <0x10480000 0x10000>;
};
combiner: interrupt-controller@10440000 {
compatible = "samsung,exynos4210-combiner";
#interrupt-cells = <2>;
interrupt-controller;
reg = <0x10440000 0x1000>;
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupt-parent = <&combiner>;
interrupts = <2 2>, <3 2>;
};
sys_reg: syscon@10010000 {
compatible = "samsung,exynos4-sysreg", "syscon";
reg = <0x10010000 0x400>;
};
pmu_system_controller: system-controller@10020000 {
compatible = "samsung,exynos4210-pmu", "syscon";
reg = <0x10020000 0x4000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
};
dsi_0: dsi@11C80000 {
compatible = "samsung,exynos4210-mipi-dsi";
reg = <0x11C80000 0x10000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_lcd0>;
phys = <&mipi_phy 1>;
phy-names = "dsim";
clocks = <&clock CLK_DSIM0>, <&clock CLK_SCLK_MIPI0>;
clock-names = "bus_clk", "sclk_mipi";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
camera {
compatible = "samsung,fimc", "simple-bus";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
#clock-cells = <1>;
clock-output-names = "cam_a_clkout", "cam_b_clkout";
ranges;
fimc_0: fimc@11800000 {
compatible = "samsung,exynos4210-fimc";
reg = <0x11800000 0x1000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC0>, <&clock CLK_SCLK_FIMC0>;
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
samsung,sysreg = <&sys_reg>;
iommus = <&sysmmu_fimc0>;
status = "disabled";
};
fimc_1: fimc@11810000 {
compatible = "samsung,exynos4210-fimc";
reg = <0x11810000 0x1000>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC1>, <&clock CLK_SCLK_FIMC1>;
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
samsung,sysreg = <&sys_reg>;
iommus = <&sysmmu_fimc1>;
status = "disabled";
};
fimc_2: fimc@11820000 {
compatible = "samsung,exynos4210-fimc";
reg = <0x11820000 0x1000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC2>, <&clock CLK_SCLK_FIMC2>;
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
samsung,sysreg = <&sys_reg>;
iommus = <&sysmmu_fimc2>;
status = "disabled";
};
fimc_3: fimc@11830000 {
compatible = "samsung,exynos4210-fimc";
reg = <0x11830000 0x1000>;
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_FIMC3>, <&clock CLK_SCLK_FIMC3>;
clock-names = "fimc", "sclk_fimc";
power-domains = <&pd_cam>;
samsung,sysreg = <&sys_reg>;
iommus = <&sysmmu_fimc3>;
status = "disabled";
};
csis_0: csis@11880000 {
compatible = "samsung,exynos4210-csis";
reg = <0x11880000 0x4000>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_CSIS0>, <&clock CLK_SCLK_CSIS0>;
clock-names = "csis", "sclk_csis";
bus-width = <4>;
power-domains = <&pd_cam>;
phys = <&mipi_phy 0>;
phy-names = "csis";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
csis_1: csis@11890000 {
compatible = "samsung,exynos4210-csis";
reg = <0x11890000 0x4000>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_CSIS1>, <&clock CLK_SCLK_CSIS1>;
clock-names = "csis", "sclk_csis";
bus-width = <2>;
power-domains = <&pd_cam>;
phys = <&mipi_phy 2>;
phy-names = "csis";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
};
};
rtc: rtc@10070000 {
compatible = "samsung,s3c6410-rtc";
reg = <0x10070000 0x100>;
interrupt-parent = <&pmu_system_controller>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_RTC>;
clock-names = "rtc";
status = "disabled";
};
keypad: keypad@100A0000 {
compatible = "samsung,s5pv210-keypad";
reg = <0x100A0000 0x100>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_KEYIF>;
clock-names = "keypad";
status = "disabled";
};
sdhci_0: sdhci@12510000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12510000 0x100>;
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SDMMC0>, <&clock CLK_SCLK_MMC0>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
};
sdhci_1: sdhci@12520000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12520000 0x100>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SDMMC1>, <&clock CLK_SCLK_MMC1>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
};
sdhci_2: sdhci@12530000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12530000 0x100>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SDMMC2>, <&clock CLK_SCLK_MMC2>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
};
sdhci_3: sdhci@12540000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12540000 0x100>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SDMMC3>, <&clock CLK_SCLK_MMC3>;
clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
};
exynos_usbphy: exynos-usbphy@125B0000 {
compatible = "samsung,exynos4210-usb2-phy";
reg = <0x125B0000 0x100>;
samsung,pmureg-phandle = <&pmu_system_controller>;
clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>;
clock-names = "phy", "ref";
#phy-cells = <1>;
status = "disabled";
};
hsotg: hsotg@12480000 {
compatible = "samsung,s3c6400-hsotg";
reg = <0x12480000 0x20000>;
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB_DEVICE>;
clock-names = "otg";
phys = <&exynos_usbphy 0>;
phy-names = "usb2-phy";
status = "disabled";
};
ehci: ehci@12580000 {
compatible = "samsung,exynos4210-ehci";
reg = <0x12580000 0x100>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB_HOST>;
clock-names = "usbhost";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phys = <&exynos_usbphy 1>;
status = "disabled";
};
port@1 {
reg = <1>;
phys = <&exynos_usbphy 2>;
status = "disabled";
};
port@2 {
reg = <2>;
phys = <&exynos_usbphy 3>;
status = "disabled";
};
};
ohci: ohci@12590000 {
compatible = "samsung,exynos4210-ohci";
reg = <0x12590000 0x100>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_USB_HOST>;
clock-names = "usbhost";
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phys = <&exynos_usbphy 1>;
status = "disabled";
};
};
i2s1: i2s@13960000 {
compatible = "samsung,s3c6410-i2s";
reg = <0x13960000 0x100>;
clocks = <&clock CLK_I2S1>;
clock-names = "iis";
#clock-cells = <1>;
clock-output-names = "i2s_cdclk1";
dmas = <&pdma1 12>, <&pdma1 11>;
dma-names = "tx", "rx";
#sound-dai-cells = <1>;
status = "disabled";
};
i2s2: i2s@13970000 {
compatible = "samsung,s3c6410-i2s";
reg = <0x13970000 0x100>;
clocks = <&clock CLK_I2S2>;
clock-names = "iis";
#clock-cells = <1>;
clock-output-names = "i2s_cdclk2";
dmas = <&pdma0 14>, <&pdma0 13>;
dma-names = "tx", "rx";
#sound-dai-cells = <1>;
status = "disabled";
};
mfc: codec@13400000 {
compatible = "samsung,mfc-v5";
reg = <0x13400000 0x10000>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_mfc>;
clocks = <&clock CLK_MFC>, <&clock CLK_SCLK_MFC>;
clock-names = "mfc", "sclk_mfc";
iommus = <&sysmmu_mfc_l>, <&sysmmu_mfc_r>;
iommu-names = "left", "right";
};
serial_0: serial@13800000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13800000 0x100>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma0 15>, <&pdma0 16>;
dma-names = "rx", "tx";
status = "disabled";
};
serial_1: serial@13810000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13810000 0x100>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma1 15>, <&pdma1 16>;
dma-names = "rx", "tx";
status = "disabled";
};
serial_2: serial@13820000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma0 17>, <&pdma0 18>;
dma-names = "rx", "tx";
status = "disabled";
};
serial_3: serial@13830000 {
compatible = "samsung,exynos4210-uart";
reg = <0x13830000 0x100>;
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_UART3>, <&clock CLK_SCLK_UART3>;
clock-names = "uart", "clk_uart_baud0";
dmas = <&pdma1 17>; //<&pdma1 18>;
dma-names = "rx", "tx";
status = "disabled";
};
i2c_0: i2c@13860000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13860000 0x100>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C0>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c0_bus>;
status = "disabled";
};
i2c_1: i2c@13870000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C1>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c1_bus>;
status = "disabled";
};
i2c_2: i2c@13880000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13880000 0x100>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C2>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c2_bus>;
status = "disabled";
};
i2c_3: i2c@13890000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x13890000 0x100>;
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C3>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c3_bus>;
status = "disabled";
};
i2c_4: i2c@138A0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138A0000 0x100>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C4>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c4_bus>;
status = "disabled";
};
i2c_5: i2c@138B0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138B0000 0x100>;
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C5>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c5_bus>;
status = "disabled";
};
i2c_6: i2c@138C0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138C0000 0x100>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C6>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c6_bus>;
status = "disabled";
};
i2c_7: i2c@138D0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-i2c";
reg = <0x138D0000 0x100>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C7>;
clock-names = "i2c";
pinctrl-names = "default";
pinctrl-0 = <&i2c7_bus>;
status = "disabled";
};
i2c_8: i2c@138E0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "samsung,s3c2440-hdmiphy-i2c";
reg = <0x138E0000 0x100>;
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_I2C_HDMI>;
clock-names = "i2c";
status = "disabled";
hdmi_i2c_phy: hdmiphy@38 {
compatible = "exynos4210-hdmiphy";
reg = <0x38>;
};
};
spi_0: spi@13920000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13920000 0x100>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 7>, <&pdma0 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_SPI0>, <&clock CLK_SCLK_SPI0>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi0_bus>;
status = "disabled";
};
spi_1: spi@13930000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13930000 0x100>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 7>, <&pdma1 6>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_SPI1>, <&clock CLK_SCLK_SPI1>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi1_bus>;
status = "disabled";
};
spi_2: spi@13940000 {
compatible = "samsung,exynos4210-spi";
reg = <0x13940000 0x100>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma0 9>, <&pdma0 8>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock CLK_SPI2>, <&clock CLK_SCLK_SPI2>;
clock-names = "spi", "spi_busclk0";
pinctrl-names = "default";
pinctrl-0 = <&spi2_bus>;
status = "disabled";
};
pwm: pwm@139D0000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x139D0000 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PWM>;
clock-names = "timers";
#pwm-cells = <3>;
status = "disabled";
};
amba {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&gic>;
ranges;
pdma0: pdma@12680000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA0>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
pdma1: pdma@12690000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12690000 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_PDMA1>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
};
mdma1: mdma@12850000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x12850000 0x1000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_MDMA>;
clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
};
};
fimd: fimd@11c00000 {
compatible = "samsung,exynos4210-fimd";
interrupt-parent = <&combiner>;
reg = <0x11c00000 0x20000>;
interrupt-names = "fifo", "vsync", "lcd_sys";
interrupts = <11 0>, <11 1>, <11 2>;
clocks = <&clock CLK_SCLK_FIMD0>, <&clock CLK_FIMD0>;
clock-names = "sclk_fimd", "fimd";
power-domains = <&pd_lcd0>;
iommus = <&sysmmu_fimd0>;
samsung,sysreg = <&sys_reg>;
status = "disabled";
};
tmu: tmu@100C0000 {
#include "exynos4412-tmu-sensor-conf.dtsi"
};
jpeg_codec: jpeg-codec@11840000 {
compatible = "samsung,exynos4210-jpeg";
reg = <0x11840000 0x1000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_JPEG>;
clock-names = "jpeg";
power-domains = <&pd_cam>;
iommus = <&sysmmu_jpeg>;
};
rotator: rotator@12810000 {
compatible = "samsung,exynos4210-rotator";
reg = <0x12810000 0x64>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_ROTATOR>;
clock-names = "rotator";
iommus = <&sysmmu_rotator>;
};
hdmi: hdmi@12D00000 {
compatible = "samsung,exynos4210-hdmi";
reg = <0x12D00000 0x70000>;
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy",
"mout_hdmi";
clocks = <&clock CLK_HDMI>, <&clock CLK_SCLK_HDMI>,
<&clock CLK_SCLK_PIXEL>, <&clock CLK_SCLK_HDMIPHY>,
<&clock CLK_MOUT_HDMI>;
phy = <&hdmi_i2c_phy>;
power-domains = <&pd_tv>;
samsung,syscon-phandle = <&pmu_system_controller>;
status = "disabled";
};
hdmicec: cec@100B0000 {
compatible = "samsung,s5p-cec";
reg = <0x100B0000 0x200>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_HDMI_CEC>;
clock-names = "hdmicec";
samsung,syscon-phandle = <&pmu_system_controller>;
hdmi-phandle = <&hdmi>;
pinctrl-names = "default";
pinctrl-0 = <&hdmi_cec>;
status = "disabled";
};
mixer: mixer@12C10000 {
compatible = "samsung,exynos4210-mixer";
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x12C10000 0x2100>, <0x12c00000 0x300>;
power-domains = <&pd_tv>;
iommus = <&sysmmu_tv>;
status = "disabled";
};
ppmu_dmc0: ppmu_dmc0@106a0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x106a0000 0x2000>;
clocks = <&clock CLK_PPMUDMC0>;
clock-names = "ppmu";
status = "disabled";
};
ppmu_dmc1: ppmu_dmc1@106b0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x106b0000 0x2000>;
clocks = <&clock CLK_PPMUDMC1>;
clock-names = "ppmu";
status = "disabled";
};
ppmu_cpu: ppmu_cpu@106c0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x106c0000 0x2000>;
clocks = <&clock CLK_PPMUCPU>;
clock-names = "ppmu";
status = "disabled";
};
ppmu_acp: ppmu_acp@10ae0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x106e0000 0x2000>;
status = "disabled";
};
ppmu_rightbus: ppmu_rightbus@112a0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x112a0000 0x2000>;
clocks = <&clock CLK_PPMURIGHT>;
clock-names = "ppmu";
status = "disabled";
};
ppmu_leftbus: ppmu_leftbus0@116a0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x116a0000 0x2000>;
clocks = <&clock CLK_PPMULEFT>;
clock-names = "ppmu";
status = "disabled";
};
ppmu_camif: ppmu_camif@11ac0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x11ac0000 0x2000>;
clocks = <&clock CLK_PPMUCAMIF>;
clock-names = "ppmu";
status = "disabled";
};
ppmu_lcd0: ppmu_lcd0@11e40000 {
compatible = "samsung,exynos-ppmu";
reg = <0x11e40000 0x2000>;
clocks = <&clock CLK_PPMULCD0>;
clock-names = "ppmu";
status = "disabled";
};
ppmu_fsys: ppmu_g3d@12630000 {
compatible = "samsung,exynos-ppmu";
reg = <0x12630000 0x2000>;
status = "disabled";
};
ppmu_image: ppmu_image@12aa0000 {
compatible = "samsung,exynos-ppmu";
reg = <0x12aa0000 0x2000>;
clocks = <&clock CLK_PPMUIMAGE>;
clock-names = "ppmu";
status = "disabled";
};
ppmu_tv: ppmu_tv@12e40000 {
compatible = "samsung,exynos-ppmu";
reg = <0x12e40000 0x2000>;
clocks = <&clock CLK_PPMUTV>;
clock-names = "ppmu";
status = "disabled";
};
ppmu_g3d: ppmu_g3d@13220000 {
compatible = "samsung,exynos-ppmu";
reg = <0x13220000 0x2000>;
clocks = <&clock CLK_PPMUG3D>;
clock-names = "ppmu";
status = "disabled";
};
ppmu_mfc_left: ppmu_mfc_left@13660000 {
compatible = "samsung,exynos-ppmu";
reg = <0x13660000 0x2000>;
clocks = <&clock CLK_PPMUMFC_L>;
clock-names = "ppmu";
status = "disabled";
};
ppmu_mfc_right: ppmu_mfc_right@13670000 {
compatible = "samsung,exynos-ppmu";
reg = <0x13670000 0x2000>;
clocks = <&clock CLK_PPMUMFC_R>;
clock-names = "ppmu";
status = "disabled";
};
sysmmu_mfc_l: sysmmu@13620000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13620000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <5 5>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MFCL>, <&clock CLK_MFC>;
power-domains = <&pd_mfc>;
#iommu-cells = <0>;
};
sysmmu_mfc_r: sysmmu@13630000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x13630000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <5 6>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_MFCR>, <&clock CLK_MFC>;
power-domains = <&pd_mfc>;
#iommu-cells = <0>;
};
sysmmu_tv: sysmmu@12E20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x12E20000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <5 4>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_TV>, <&clock CLK_MIXER>;
power-domains = <&pd_tv>;
#iommu-cells = <0>;
};
sysmmu_fimc0: sysmmu@11A20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11A20000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <4 2>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_FIMC0>, <&clock CLK_FIMC0>;
power-domains = <&pd_cam>;
#iommu-cells = <0>;
};
sysmmu_fimc1: sysmmu@11A30000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11A30000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <4 3>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_FIMC1>, <&clock CLK_FIMC1>;
power-domains = <&pd_cam>;
#iommu-cells = <0>;
};
sysmmu_fimc2: sysmmu@11A40000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11A40000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <4 4>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_FIMC2>, <&clock CLK_FIMC2>;
power-domains = <&pd_cam>;
#iommu-cells = <0>;
};
sysmmu_fimc3: sysmmu@11A50000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11A50000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <4 5>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_FIMC3>, <&clock CLK_FIMC3>;
power-domains = <&pd_cam>;
#iommu-cells = <0>;
};
sysmmu_jpeg: sysmmu@11A60000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11A60000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <4 6>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_JPEG>, <&clock CLK_JPEG>;
power-domains = <&pd_cam>;
#iommu-cells = <0>;
};
sysmmu_rotator: sysmmu@12A30000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x12A30000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <5 0>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_ROTATOR>, <&clock CLK_ROTATOR>;
#iommu-cells = <0>;
};
sysmmu_fimd0: sysmmu@11E20000 {
compatible = "samsung,exynos-sysmmu";
reg = <0x11E20000 0x1000>;
interrupt-parent = <&combiner>;
interrupts = <5 2>;
clock-names = "sysmmu", "master";
clocks = <&clock CLK_SMMU_FIMD0>, <&clock CLK_FIMD0>;
power-domains = <&pd_lcd0>;
#iommu-cells = <0>;
};
sss: sss@10830000 {
compatible = "samsung,exynos4210-secss";
reg = <0x10830000 0x300>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock CLK_SSS>;
clock-names = "secss";
};
prng: rng@10830400 {
compatible = "samsung,exynos4-rng";
reg = <0x10830400 0x200>;
clocks = <&clock CLK_SSS>;
clock-names = "secss";
};
};5、对设备树进行编译
返回到内核源码文件目录，输入下图所示命令，如下图所示：
等待编译结果如下图所示：
如上两图所示，即为编译生成的设备树 dtb 文件“exynos4412-itop-elite.dtb” 和内核镜像uImage 。
有关生成的zImage及uImage文件说明：
openEuler 是由开放原子开源基金会孵化的全场景开源操作系统项目，面向数字基础设施四大核心场景（服务器、云计算、边缘计算、嵌入式），全面支持 ARM、x86、RISC-V、loongArch、PowerPC、SW-64 等多样性计算架构
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